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[/] [light8080/] [trunk/] [vhdl/] [light8080.vhdl] - Rev 73

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Rev Log message Author Age Path
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly		 ja_rd 4650d 05h /light8080/trunk/vhdl/light8080.vhdl
54 BUG FIX: XOR operations wre not clearing CY and ACY ja_rd 5231d 18h /light8080/trunk/vhdl/light8080.vhdl
49 fixed: IE now enables interrupts after a 1-instruction delay
(it was enabling interrupts immediately)		 ja_rd 5587d 19h /light8080/trunk/vhdl/light8080.vhdl
39 fixed: int request (intr) can now be wider than 1 cycle ja_rd 5588d 11h /light8080/trunk/vhdl/light8080.vhdl
31 New directory structure. root 5719d 15h /light8080/trunk/vhdl/light8080.vhdl
19 Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances)
Added an output to the core to mark the fetch cycle of all instructions
Started to add timing diagrams		 ja_rd 5739d 21h /light8080/trunk/vhdl/light8080.vhdl
10 minor edits, comments clarified ja_rd 5853d 14h /light8080/trunk/vhdl/light8080.vhdl
6 microcode bug in INR M, #setacy flag missing ja_rd 5923d 00h /light8080/trunk/vhdl/light8080.vhdl
4 light8080.vhdl

comments in header corrected (they were obsolete)		 ja_rd 6202d 02h /light8080/trunk/vhdl/light8080.vhdl
3 added author line and license file ja_rd 6208d 17h /light8080/trunk/vhdl/light8080.vhdl
2 initial commit ja_rd 6210d 04h /light8080/trunk/vhdl/light8080.vhdl

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