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[/] [light8080/] [trunk/] [vhdl/] [light8080.vhdl] - Rev 90

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Rev Log message Author Age Path
79 DAA logic fixed and simplified ja_rd 4609d 00h /light8080/trunk/vhdl/light8080.vhdl
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly		 ja_rd 4673d 10h /light8080/trunk/vhdl/light8080.vhdl
54 BUG FIX: XOR operations wre not clearing CY and ACY ja_rd 5255d 00h /light8080/trunk/vhdl/light8080.vhdl
49 fixed: IE now enables interrupts after a 1-instruction delay
(it was enabling interrupts immediately)		 ja_rd 5611d 00h /light8080/trunk/vhdl/light8080.vhdl
39 fixed: int request (intr) can now be wider than 1 cycle ja_rd 5611d 16h /light8080/trunk/vhdl/light8080.vhdl
31 New directory structure. root 5742d 20h /light8080/trunk/vhdl/light8080.vhdl
19 Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances)
Added an output to the core to mark the fetch cycle of all instructions
Started to add timing diagrams		 ja_rd 5763d 02h /light8080/trunk/vhdl/light8080.vhdl
10 minor edits, comments clarified ja_rd 5876d 19h /light8080/trunk/vhdl/light8080.vhdl
6 microcode bug in INR M, #setacy flag missing ja_rd 5946d 05h /light8080/trunk/vhdl/light8080.vhdl
4 light8080.vhdl

comments in header corrected (they were obsolete)		 ja_rd 6225d 07h /light8080/trunk/vhdl/light8080.vhdl
3 added author line and license file ja_rd 6231d 22h /light8080/trunk/vhdl/light8080.vhdl
2 initial commit ja_rd 6233d 09h /light8080/trunk/vhdl/light8080.vhdl

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