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[/] [mdct/] [trunk/] [source/] [DCT2D.VHD] - Rev 27

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Rev Log message Author Age Path
27 Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area. mikel262 5723d 16h /mdct/trunk/source/DCT2D.VHD
24 New directory structure. root 5731d 10h /mdct/trunk/source/DCT2D.VHD
18 Minor fixes. This release is FPGA proven. mikel262 6758d 13h /mdct/trunk/source/DCT2D.VHD
15 Redesigned. Fully pipelined, always ready for data design mikel262 6780d 11h /mdct/trunk/source/DCT2D.VHD
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6784d 10h /mdct/trunk/source/DCT2D.VHD
7 documentation update. minor area optimization. mikel262 6789d 09h /mdct/trunk/source/DCT2D.VHD
4 area optimization - 100 slices less mikel262 6790d 10h /mdct/trunk/source/DCT2D.VHD
2 Initial import (Beta Release) mikel262 6790d 22h /mdct/trunk/source/DCT2D.VHD

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