URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [tests.v] - Rev 28

Rev	Log message	Author	Age	Path
28	New directory structure.	root	5743d 08h	/mem_ctrl/trunk/bench/verilog/tests.v
23	* empty log message *	rudi	8347d 20h	/mem_ctrl/trunk/bench/verilog/tests.v
16	- More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8401d 07h	/mem_ctrl/trunk/bench/verilog/tests.v
15	Just minor test bench update, syncing all the files.	rudi	8417d 08h	/mem_ctrl/trunk/bench/verilog/tests.v
14	Minor fixes to testbench ...	rudi	8419d 07h	/mem_ctrl/trunk/bench/verilog/tests.v
10	Fixed the TMS register setup to be tight and correct.	rudi	8489d 07h	/mem_ctrl/trunk/bench/verilog/tests.v
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Removed "Refresh Early" configuration	rudi	8512d 01h	/mem_ctrl/trunk/bench/verilog/tests.v
4	1) Changed Directory Structure 2) Fixed several minor bugs	rudi	8524d 02h	/mem_ctrl/trunk/bench/verilog/tests.v