URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_rf.v] - Rev 28

Rev	Log message	Author	Age	Path
28	New directory structure.	root	5739d 22h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
22	Fixed several minor bugs, cleaned up the code further ...	rudi	8344d 10h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
20	- Fixed combinatorial loops in synthesis - Fixed byte select bug	rudi	8375d 18h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
18	- Made some changes not to expect clock during reset ...	rudi	8385d 20h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
16	- More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8397d 21h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
13	Fixed Register reads Tightened up timing for register rd/wr	rudi	8453d 20h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
12	Changed Reset to be active high and async.	rudi	8463d 23h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Removed "Refresh Early" configuration	rudi	8508d 15h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v
4	1) Changed Directory Structure 2) Fixed several minor bugs	rudi	8520d 16h	/mem_ctrl/trunk/rtl/verilog/mc_rf.v