URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_top.v] - Rev 28

Rev	Log message	Author	Age	Path
28	New directory structure.	root	5727d 19h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
22	Fixed several minor bugs, cleaned up the code further ...	rudi	8332d 07h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
20	- Fixed combinatorial loops in synthesis - Fixed byte select bug	rudi	8363d 15h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
16	- More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8385d 18h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
11	* empty log message *	rudi	8465d 06h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
9	Many fixes for minor bugs that showed up in gate level simulations.	rudi	8473d 18h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Removed "Refresh Early" configuration	rudi	8496d 12h	/mem_ctrl/trunk/rtl/verilog/mc_top.v
4	1) Changed Directory Structure 2) Fixed several minor bugs	rudi	8508d 12h	/mem_ctrl/trunk/rtl/verilog/mc_top.v