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[/] [minimips_superscalar/] [tags/] [P0/] [sources/] [minimips.vhd] - Rev 30

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Rev Log message Author Age Path
18 clock_gate.vhd: removed.
minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.
mcafruni 1913d 15h /minimips_superscalar/tags/P0/sources/minimips.vhd
4 It needs to be tested on more useful and real benchmarks to reveal possible instruction sequences not supported by the architecture. Suggestions are welcome. mcafruni 2004d 13h /minimips_superscalar/tags/P0/sources/minimips.vhd

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