URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] [minsoc_bench_defines.v] - Rev 161

Rev	Log message	Author	Age	Path
147	Updating minsoc_bench.v to correctly acquire uart data. Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed. -Eth and Uart firmwares also had a carriage return after the end of line, also removed. Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd. minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.	rfajardo	4744d 22h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4765d 19h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
109	Creating a branche for release candidate 1.0.	rfajardo	4772d 15h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4821d 03h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v