URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] [minsoc_bench.v] - Rev 171

Rev	Log message	Author	Age	Path
148	Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness.	rfajardo	4760d 07h	/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v
147	Updating minsoc_bench.v to correctly acquire uart data. Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed. -Eth and Uart firmwares also had a carriage return after the end of line, also removed. Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd. minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.	rfajardo	4760d 08h	/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4776d 11h	/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v