URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [Makefile] - Rev 109

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4778d 18h	/minsoc/branches/rc-1.0/prj/Makefile
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4786d 04h	/minsoc/branches/rc-1.0/prj/Makefile
96	Some files needed for Altera synthesis	javieralso	4823d 16h	/minsoc/branches/rc-1.0/prj/Makefile
95	Makefile for Altera FPGAs fixed	javieralso	4824d 19h	/minsoc/branches/rc-1.0/prj/Makefile
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4828d 21h	/minsoc/branches/rc-1.0/prj/Makefile
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4828d 22h	/minsoc/branches/rc-1.0/prj/Makefile