OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [scripts/] [simverilog.sh] - Rev 109

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 4778d 20h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4779d 00h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4786d 06h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4828d 08h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4828d 23h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4829d 01h /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.