URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [scripts/] [simvhdl.sh] - Rev 109

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4763d 04h	/minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh
108	Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files. Icarus Verilog and Altera synthesis are working as well. Job done!	rfajardo	4763d 07h	/minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4770d 13h	/minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh