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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [scripts/] [xilinxprj.sh] - Rev 129

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Rev Log message Author Age Path
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4805d 11h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
109 Creating a branche for release candidate 1.0. rfajardo 4805d 13h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4805d 16h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4855d 00h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4855d 16h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4855d 17h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh

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