URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [altera_pll.v] - Rev 117

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4784d 22h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
63	Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something.	rfajardo	4965d 01h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4965d 08h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
56	Macros for all Altera family devices and pll instantiation	javieralso	4972d 20h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
52	Altera ALTPLL Megafunction Instantiation	javieralso	4982d 21h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v