URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Rev 127

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4805d 22h	/minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4986d 07h	/minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
56	Macros for all Altera family devices and pll instantiation	javieralso	4993d 19h	/minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
52	Altera ALTPLL Megafunction Instantiation	javieralso	5003d 21h	/minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5574d 06h	/minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v