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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [minsoc_startup/] [spi_clgen.v] - Rev 171

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109 Creating a branche for release candidate 1.0. rfajardo 4788d 08h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5556d 16h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v

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