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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [timescale.v] - Rev 129

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4805d 14h	/minsoc/branches/rc-1.0/rtl/verilog/timescale.v
70	Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it. Removing timescale definition of minsoc_bench_defines.v files. Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed: -pli ../../bench/verilog/vpi/jp-io-vpi.so to: -pli ../../bench/verilog/vpi/jp-io-vpi.dll These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.	rfajardo	4975d 00h	/minsoc/branches/rc-1.0/rtl/verilog/timescale.v