URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 160

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4762d 12h	/minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4812d 15h	/minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4942d 21h	/minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v