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[/] [minsoc/] [branches/] [rc-1.0/] [sim/] [modelsim/] [compile_design.bat] - Rev 110

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109 Creating a branche for release candidate 1.0. rfajardo 4759d 16h /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4767d 02h /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4809d 21h /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.		 rfajardo 4928d 22h /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat		 rfajardo 4928d 23h /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat

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