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[/] [minsoc/] [branches/] [verilator/] [backend/] [altera_3c25_board/] [configure] - Rev 139

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139 Creating a verilator branche. rfajardo 4783d 16h /minsoc/branches/verilator/backend/altera_3c25_board/configure
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4809d 12h /minsoc/branches/verilator/backend/altera_3c25_board/configure
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4810d 05h /minsoc/branches/verilator/backend/altera_3c25_board/configure
109 Creating a branche for release candidate 1.0. rfajardo 4810d 07h /minsoc/branches/verilator/backend/altera_3c25_board/configure
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4810d 17h /minsoc/branches/verilator/backend/altera_3c25_board/configure
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4854d 18h /minsoc/branches/verilator/backend/altera_3c25_board/configure
96 Some files needed for Altera synthesis javieralso 4855d 04h /minsoc/branches/verilator/backend/altera_3c25_board/configure
95 Makefile for Altera FPGAs fixed javieralso 4856d 07h /minsoc/branches/verilator/backend/altera_3c25_board/configure
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4858d 19h /minsoc/branches/verilator/backend/altera_3c25_board/configure

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