URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [backend/] [altera_3c25_board/] [minsoc_bench_defines.v] - Rev 166

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4759d 18h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_bench_defines.v
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4779d 12h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_bench_defines.v
109	Creating a branche for release candidate 1.0.	rfajardo	4786d 08h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_bench_defines.v
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4834d 20h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_bench_defines.v