URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [backend/] [altera_3c25_board/] [minsoc_defines.v] - Rev 160

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4739d 09h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
109	Creating a branche for release candidate 1.0.	rfajardo	4766d 00h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
99	backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails.	rfajardo	4810d 10h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
95	Makefile for Altera FPGAs fixed	javieralso	4812d 01h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4814d 12h	/minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v