URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench.v] - Rev 147

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4783d 14h	/minsoc/branches/verilator/bench/verilog/minsoc_bench.v
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4798d 14h	/minsoc/branches/verilator/bench/verilog/minsoc_bench.v