URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_clock.v] - Rev 174

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4785d 15h	/minsoc/branches/verilator/bench/verilog/minsoc_bench_clock.v
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4804d 11h	/minsoc/branches/verilator/bench/verilog/minsoc_bench_clock.v
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4805d 01h	/minsoc/branches/verilator/bench/verilog/minsoc_bench_clock.v
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4805d 01h	/minsoc/branches/verilator/bench/verilog/minsoc_bench_clock.v