| Rev |
Log message |
Author |
Age |
Path |
| 139 |
Creating a verilator branche. |
rfajardo |
4751d 22h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 133 |
Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.
Applying Rubén Diez patch to avoid warnings on firmware load for simulation. |
rfajardo |
4766d 22h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 131 |
Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. |
rfajardo |
4770d 18h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 130 |
minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. |
rfajardo |
4770d 20h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 129 |
Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready |
rfajardo |
4771d 07h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 128 |
Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. |
rfajardo |
4771d 08h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 127 |
Removing redundant simulation output. |
rfajardo |
4771d 14h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 126 |
Updating information about simulation time for Ethernet test. |
rfajardo |
4771d 14h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 125 |
Adjusting testbench messages. Creating tasks for firmware tests. |
rfajardo |
4771d 15h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 124 |
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. |
rfajardo |
4771d 16h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 123 |
Renaming reg final to firmware_size. Final is a keyword for Verilator. |
rfajardo |
4771d 21h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4778d 12h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 71 |
Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v
modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a
Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now. |
rfajardo |
4947d 21h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 60 |
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.
minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition. |
rfajardo |
4959d 09h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4959d 10h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 28 |
1) Period calculations through 1/freq on testbench use now a numerator definition in order to extract nano seconds of the divisions. Previously the number 1e9 was being repeatedly typed as numerator, now FREQ_NUM_FOR_NS is used.
2) There is a possibility of enabling the GENERIC_CLOCK_DIVISION for the testbench, so that you can test the outcome of different system clock inputs and internal clock adjustments. To do so, NO_CLOCK_DIVISION definition of minsoc_bench_defines.v has to be commented out.
-This also requested the initialization of the internal registers clk_int and clock_divisor of the minsoc_clock_manager.v, this is made by the testbench in case the NO_CLOCK_DIVISION definition is NOT defined.
3) Howto part of implementing Ethernet for the Spartan3E Starter Kit has been completely described. (Chapter 7, subitem 3) |
rfajardo |
5317d 17h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 17 |
Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module. |
rfajardo |
5486d 17h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 11 |
External interrupt processing was being run multiple times because:
-external level interrupts have to be cleared
-internal interrupt status register has to be cleared
Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween.
Solution:
-move status register reset to end of interrupt handler instead of beginning.
Testbench signal uart_srx initialized now. |
rfajardo |
5511d 17h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 10 |
Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.
With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.
minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary. |
rfajardo |
5525d 17h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
| 9 |
Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC. |
rfajardo |
5527d 15h |
/minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v |
