URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Rev 147

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4746d 05h	/minsoc/branches/verilator/bench/verilog/vpi/dbg_comm_vpi.v
109	Creating a branche for release candidate 1.0.	rfajardo	4772d 20h	/minsoc/branches/verilator/bench/verilog/vpi/dbg_comm_vpi.v
71	Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.	rfajardo	4942d 05h	/minsoc/branches/verilator/bench/verilog/vpi/dbg_comm_vpi.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5541d 04h	/minsoc/branches/verilator/bench/verilog/vpi/dbg_comm_vpi.v