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139 Creating a verilator branche. rfajardo 4731d 19h /minsoc/branches/verilator/doc/lgpl-3.0.txt
109 Creating a branche for release candidate 1.0. rfajardo 4758d 09h /minsoc/branches/verilator/doc/lgpl-3.0.txt
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5526d 17h /minsoc/branches/verilator/doc/lgpl-3.0.txt

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