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[/] [minsoc/] [branches/] [verilator/] [prj/] [Makefile] - Rev 174

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Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4785d 00h	/minsoc/branches/verilator/prj/Makefile
113	minsoc-install.sh & minsoc-configure.sh: -aware of location of configure.sh script configure.sh: -does not block on patch error spartan3e_starter_kit & spartan3e_starter_kit_eth: -or1200_defines.v updated prj: -src/blackboxes/or1200_top.v adjusted to or1200_rel1 -Makefile had a typo regarding altera vhdl files	rfajardo	4810d 20h	/minsoc/branches/verilator/prj/Makefile
110	Fixing several minor issues with the system: -minsoc-install splitted into installation and configuration -minsoc-configure.sh can be used to configure a fresh checked out system -configure script used by both minsoc-configure.sh and minsoc-install.sh to configure -rtl/verilog: svn externals fixed -or1200 rolled back to release-1.0 -prj/scripts: -Makefile has been used by simulation to differentiate project definition of vhdl and verilog files -Altera was differentiating it in script -now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation. -altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files. -prj/src: or1200_top.prj downdated to definition of or1200_v1	rfajardo	4811d 12h	/minsoc/branches/verilator/prj/Makefile
109	Creating a branche for release candidate 1.0.	rfajardo	4811d 14h	/minsoc/branches/verilator/prj/Makefile
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4819d 00h	/minsoc/branches/verilator/prj/Makefile
96	Some files needed for Altera synthesis	javieralso	4856d 12h	/minsoc/branches/verilator/prj/Makefile
95	Makefile for Altera FPGAs fixed	javieralso	4857d 15h	/minsoc/branches/verilator/prj/Makefile
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4861d 17h	/minsoc/branches/verilator/prj/Makefile
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4861d 19h	/minsoc/branches/verilator/prj/Makefile

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