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[/] [minsoc/] [branches/] [verilator/] [prj/] [scripts/] [altvhdprj.sh] - Rev 159

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4778d 23h /minsoc/branches/verilator/prj/scripts/altvhdprj.sh
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 4805d 11h /minsoc/branches/verilator/prj/scripts/altvhdprj.sh

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