URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [scripts/] [xilinxxst.sh] - Rev 173

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4699d 08h	/minsoc/branches/verilator/prj/scripts/xilinxxst.sh
109	Creating a branche for release candidate 1.0.	rfajardo	4725d 23h	/minsoc/branches/verilator/prj/scripts/xilinxxst.sh
108	Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files. Icarus Verilog and Altera synthesis are working as well. Job done!	rfajardo	4726d 02h	/minsoc/branches/verilator/prj/scripts/xilinxxst.sh
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4776d 02h	/minsoc/branches/verilator/prj/scripts/xilinxxst.sh
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4776d 03h	/minsoc/branches/verilator/prj/scripts/xilinxxst.sh