URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [blackboxes/] [or1200_top.v] - Rev 163

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4744d 06h	/minsoc/branches/verilator/prj/src/blackboxes/or1200_top.v
113	minsoc-install.sh & minsoc-configure.sh: -aware of location of configure.sh script configure.sh: -does not block on patch error spartan3e_starter_kit & spartan3e_starter_kit_eth: -or1200_defines.v updated prj: -src/blackboxes/or1200_top.v adjusted to or1200_rel1 -Makefile had a typo regarding altera vhdl files	rfajardo	4770d 02h	/minsoc/branches/verilator/prj/src/blackboxes/or1200_top.v
109	Creating a branche for release candidate 1.0.	rfajardo	4770d 20h	/minsoc/branches/verilator/prj/src/blackboxes/or1200_top.v
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4821d 00h	/minsoc/branches/verilator/prj/src/blackboxes/or1200_top.v
63	Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something.	rfajardo	4950d 22h	/minsoc/branches/verilator/prj/src/blackboxes/or1200_top.v