URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [minsoc_bench.prj] - Rev 163

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4744d 03h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4759d 04h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4762d 23h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4763d 14h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj
109	Creating a branche for release candidate 1.0.	rfajardo	4770d 18h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4820d 20h	/minsoc/branches/verilator/prj/src/minsoc_bench.prj