URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [or1200_top.prj] - Rev 174

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4785d 15h	/minsoc/branches/verilator/prj/src/or1200_top.prj
110	Fixing several minor issues with the system: -minsoc-install splitted into installation and configuration -minsoc-configure.sh can be used to configure a fresh checked out system -configure script used by both minsoc-configure.sh and minsoc-install.sh to configure -rtl/verilog: svn externals fixed -or1200 rolled back to release-1.0 -prj/scripts: -Makefile has been used by simulation to differentiate project definition of vhdl and verilog files -Altera was differentiating it in script -now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation. -altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files. -prj/src: or1200_top.prj downdated to definition of or1200_v1	rfajardo	4812d 04h	/minsoc/branches/verilator/prj/src/or1200_top.prj
109	Creating a branche for release candidate 1.0.	rfajardo	4812d 06h	/minsoc/branches/verilator/prj/src/or1200_top.prj
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4862d 10h	/minsoc/branches/verilator/prj/src/or1200_top.prj