URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [minsoc_startup/] [spi_top.v] - Rev 167

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4779d 19h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_top.v
109	Creating a branche for release candidate 1.0.	rfajardo	4806d 09h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_top.v
12	1) spi_top.v: -TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you) 2) minsoc howto extended to: -synthesis of minsoc for Spartan3E Starter Kit with Ethernet 3) spartan3e_starter_kit.ucf changed: -it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.	rfajardo	5532d 10h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_top.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5574d 17h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_top.v