URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 159

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4778d 23h	/minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
109	Creating a branche for release candidate 1.0.	rfajardo	4805d 13h	/minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4855d 16h	/minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4985d 22h	/minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v