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[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] [compile_design.bat] - Rev 144

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139 Creating a verilator branche. rfajardo 4731d 16h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4757d 06h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4757d 10h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
109 Creating a branche for release candidate 1.0. rfajardo 4758d 06h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4765d 15h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4808d 10h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.		 rfajardo 4927d 12h /minsoc/branches/verilator/sim/modelsim/compile_design.bat
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat		 rfajardo 4927d 13h /minsoc/branches/verilator/sim/modelsim/compile_design.bat

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