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[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] [compile_design.sh] - Rev 144

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139 Creating a verilator branche. rfajardo 4731d 16h /minsoc/branches/verilator/sim/modelsim/compile_design.sh
109 Creating a branche for release candidate 1.0. rfajardo 4758d 06h /minsoc/branches/verilator/sim/modelsim/compile_design.sh
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4765d 15h /minsoc/branches/verilator/sim/modelsim/compile_design.sh
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4808d 10h /minsoc/branches/verilator/sim/modelsim/compile_design.sh
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.		 rfajardo 4927d 16h /minsoc/branches/verilator/sim/modelsim/compile_design.sh

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