URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [branches/] [verilator/] [sim/] [run/] [run_bench] - Rev 139

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4752d 10h	/minsoc/branches/verilator/sim/run/run_bench
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4767d 11h	/minsoc/branches/verilator/sim/run/run_bench
109	Creating a branche for release candidate 1.0.	rfajardo	4779d 01h	/minsoc/branches/verilator/sim/run/run_bench
30	minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek. howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file. Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.	rfajardo	5275d 11h	/minsoc/branches/verilator/sim/run/run_bench
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5547d 09h	/minsoc/branches/verilator/sim/run/run_bench