URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [sw/] [support/] [int.c] - Rev 160

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4735d 21h	/minsoc/branches/verilator/sw/support/int.c
109	Creating a branche for release candidate 1.0.	rfajardo	4762d 11h	/minsoc/branches/verilator/sw/support/int.c
55	Adjusting Makefiles to compile correctly with new firmware updates. 1) except.o not included into libsupport.a. 2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around) 3) int.c was not being compiled because of a #ifdef which is not set anywhere	rfajardo	4951d 17h	/minsoc/branches/verilator/sw/support/int.c
53	Indentation, deleting redundant files and adding externals	ConX.	4951d 20h	/minsoc/branches/verilator/sw/support/int.c
11	External interrupt processing was being run multiple times because: -external level interrupts have to be cleared -internal interrupt status register has to be cleared Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween. Solution: -move status register reset to end of interrupt handler instead of beginning. Testbench signal uart_srx initialized now.	rfajardo	5495d 16h	/minsoc/branches/verilator/sw/support/int.c
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5530d 20h	/minsoc/branches/verilator/sw/support/int.c