URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [sw/] [utils/] [bin2hex.c] - Rev 169

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4780d 17h	/minsoc/branches/verilator/sw/utils/bin2hex.c
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4795d 17h	/minsoc/branches/verilator/sw/utils/bin2hex.c
109	Creating a branche for release candidate 1.0.	rfajardo	4807d 07h	/minsoc/branches/verilator/sw/utils/bin2hex.c
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5575d 15h	/minsoc/branches/verilator/sw/utils/bin2hex.c