OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [utils/] [minsoc_wb_32_8_bridge.v] - Rev 175

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4732d 04h /minsoc/branches/verilator/utils/minsoc_wb_32_8_bridge.v
109 Creating a branche for release candidate 1.0. rfajardo 4758d 18h /minsoc/branches/verilator/utils/minsoc_wb_32_8_bridge.v
36 utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect.
-adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess.

sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.

sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores.

sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead.

Documentation:
-FAQ extended:
-table of contents
-explanation of how to use the 32 to 8 bit Wishbone bridge
-how to make adv_jtag_bridge work without privilege requirement for xess or xpc3
-explanation of locking problem of xpc_usb cable
-explanation of what to do if the cable is built on-board
-INSTALL:
-patching of gdb only required if version is 6.8, explanation on FAQ now.
-HOWTO:
-instruct to compile drivers library
-remove line numbers information on what to edit, better leave it to be found only by the informed context.
-adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement.		 rfajardo 5120d 21h /minsoc/branches/verilator/utils/minsoc_wb_32_8_bridge.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.