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[/] [minsoc/] [trunk/] [backend/] [altera_3c25_board/] [minsoc_defines.v] - Rev 175

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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.		 rfajardo 4686d 14h /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4802d 00h /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v
95 Makefile for Altera FPGAs fixed javieralso 4803d 14h /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4806d 02h /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v

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