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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [configure] - Rev 165

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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.		 rfajardo 4707d 03h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
144 Updating configure scripts. Calling make into the right directories now. rfajardo 4751d 11h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.		 rfajardo 4751d 12h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4751d 12h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4778d 13h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4822d 14h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
87 Synchronizing scripts to behave exactly the same. rfajardo 4828d 07h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
86 Updating configure script messages. rfajardo 4828d 07h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4828d 07h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.		 rfajardo 4952d 04h /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure

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