URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [minsoc_bench_defines.v] - Rev 131

Rev	Log message	Author	Age	Path
70	Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it. Removing timescale definition of minsoc_bench_defines.v files. Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed: -pli ../../bench/verilog/vpi/jp-io-vpi.so to: -pli ../../bench/verilog/vpi/jp-io-vpi.dll These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.	rfajardo	4948d 12h	/minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v
69	backend update: -minsoc_bench_defines.v -gcc-opt.mk Both files should now be under minsoc/backend to proper system functionality. backend subdirectories have been given those files. Configure script updated accordingly. They are searched there from system scripts and Makefiles. -sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory. -sw/support/Makefile.inc now references to gcc-opt.mk inside backend. backend/spartan3e_starter_kit_eth: -It is the system configuration for Spartan 3E Starter Kit with Ethernet.	rfajardo	4953d 04h	/minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v