URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_bench.v] - Rev 167

Rev	Log message	Author	Age	Path
162	Tasks don't have parenthesis. This is only used for ports on modules. This was a mistake from my part.	rfajardo	4719d 22h	/minsoc/trunk/bench/verilog/minsoc_bench.v
149	Merging differences of release candidate 1.0 revision 140:148 with trunk.	rfajardo	4773d 04h	/minsoc/trunk/bench/verilog/minsoc_bench.v
141	Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days.	rfajardo	4779d 03h	/minsoc/trunk/bench/verilog/minsoc_bench.v
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4794d 04h	/minsoc/trunk/bench/verilog/minsoc_bench.v