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[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Rev 8

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2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5530d 12h /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v

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