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[/] [minsoc/] [trunk/] [prj/] [scripts/] [simverilog.sh] - Rev 169

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Rev	Log message	Author	Age	Path
141	Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days.	rfajardo	4755d 10h	/minsoc/trunk/prj/scripts/simverilog.sh
108	Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files. Icarus Verilog and Altera synthesis are working as well. Job done!	rfajardo	4782d 04h	/minsoc/trunk/prj/scripts/simverilog.sh
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4789d 10h	/minsoc/trunk/prj/scripts/simverilog.sh
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4831d 12h	/minsoc/trunk/prj/scripts/simprj.sh
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4832d 04h	/minsoc/trunk/prj/scripts/simprj.sh
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4832d 05h	/minsoc/trunk/prj/scripts/simprj.sh

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