URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Rev 163

Rev	Log message	Author	Age	Path
158	Adding de2_115_board port, thanks to Richard Hasha. Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha. Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized: -Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers. Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration. prj/srcs extended to include jsp and interconnec_defines.v. spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.	rfajardo	4696d 23h	/minsoc/trunk/prj/src/minsoc_top.prj
89	minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now.	rfajardo	4818d 02h	/minsoc/trunk/prj/src/minsoc_top.prj
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4818d 02h	/minsoc/trunk/prj/src/minsoc_top.prj
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4818d 03h	/minsoc/trunk/prj/src/minsoc_top.prj