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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Rev 68

Rev	Log message	Author	Age	Path
7	Some changes: -wb_cabs removed from minsoc_top.v and minsoc_tc_top.v -added reset polarity control to minsoc_defines.v through: -POSITIVE_RESET -NEGATIVE_RESET -minsoc_onchip_ram_top.v does not use minsoc_onchip_ram.v oe signals (output enable) anymore, which are implemented as tristate buffers. Now minsoc_onchip_ram_top.v has a generated MUX, which has an arbitrary number of inputs and 1 output. Input are the internal output of the onchip_rams, output the wb_dat_o.	rfajardo	5525d 23h	/minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v
6	No implementation relevant changes. Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge. Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.	rfajardo	5530d 05h	/minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5540d 03h	/minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v