URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_tc_top.v] - Rev 168

Rev	Log message	Author	Age	Path
163	Adjusting internal initiator array widths. They were 1 bit too large. Thanks to R. Diez report. These arrays abstract the complete initiator inputs. This way it is easier to route and arbiter using a single input. Also removing 2 sequential delays. I didn't design them, so I can't tell if they were really useful/good.	rfajardo	4670d 17h	/minsoc/trunk/rtl/verilog/minsoc_tc_top.v
7	Some changes: -wb_cabs removed from minsoc_top.v and minsoc_tc_top.v -added reset polarity control to minsoc_defines.v through: -POSITIVE_RESET -NEGATIVE_RESET -minsoc_onchip_ram_top.v does not use minsoc_onchip_ram.v oe signals (output enable) anymore, which are implemented as tristate buffers. Now minsoc_onchip_ram_top.v has a generated MUX, which has an arbitrary number of inputs and 1 output. Input are the internal output of the onchip_rams, output the wb_dat_o.	rfajardo	5516d 11h	/minsoc/trunk/rtl/verilog/minsoc_tc_top.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5530d 15h	/minsoc/trunk/rtl/verilog/minsoc_tc_top.v